Digital ASIC Designer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, is a leading scientific research institution established in 195

• It is located in Geneva, Switzerland, and is known for its groundbreaking work in particle physics. CERN operates with a diverse workforce of over 2,500 employees and collaborates with thousands of scientists from around the world. The organization is dedicated to pushing the frontiers of science and technology, fostering innovation, and promoting collaboration among professionals from various fields including engineering, technical, scientific, and administrative roles. CERN's mission is to uncover the fundamental nature of the universe, and it values diversity and inclusion as core principles in its operations.

Job Overview:
The Digital ASIC Designer position at CERN's EP-ESE-ME section involves the development of a radiation-tolerant microcontroller ASIC intended for future particle physics detectors and accelerator systems. The successful candidate will engage in a comprehensive development cycle that includes defining requirements, system architecture, implementation, verification, and post-silicon validation. The role requires a strong understanding of digital logic design and experience with digital IC design, particularly in the context of radiation environments. The project utilizes an open-source RISC-V processing core and the CERN SOCRATES framework, emphasizing the need for robust and reliable embedded electronics capable of operating under challenging conditions. The position offers an opportunity to contribute to cutting-edge research and technology in the field of particle physics.

Duties and Responsibilities:
The responsibilities of the Digital ASIC Designer include analyzing application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC. The designer will contribute to the architecture, design, and validation of the ASIC, which will be implemented in either 65 nm or 28 nm CMOS technology. Additionally, the role involves supporting the definition of the SoC architecture, selecting and configuring an appropriate RISC-V processing core, and designing, integrating, and validating peripheral IP blocks within the CERN SOCRATES framework. The designer will apply fault-tolerant design methodologies, participate in design verification activities, and contribute to post-silicon testing, characterization, and validation following chip fabrication.

Required Qualifications:
Candidates must possess a strong understanding of digital logic design and solid experience with digital IC design and RTL development, particularly using Verilog or SystemVerilog. Familiarity with standard ASIC design flows, including synthesis, place and route, and timing closure, is essential. Knowledge of RISC-V architecture and its ecosystem, as well as experience with microcontroller-based embedded systems development, including firmware programming in C and peripheral interfacing, is required. Additional skills in scripting and automation (Python or equivalent) and a working knowledge of Linux/Unix environments are also necessary. Candidates should demonstrate curiosity and a willingness to learn in a multidisciplinary environment, along with the ability to work independently and collaboratively within a team.

Educational Background:
The position requires candidates to be nationals of a CERN Member or Associate Member State and to have a professional background in Electronics Engineering or a related field. Applicants should hold either a Master's degree with 2 to 6 years of post-graduation professional experience or a PhD with no more than 3 years of post-graduation professional experience. It is important that candidates have not previously held a CERN fellow or graduate contract.

Experience:
Candidates should have a professional background that aligns with the requirements of the position, specifically in the field of Electronics Engineering. The experience level required includes 2 to 6 years of post-graduation professional experience for those with a Master's degree, or up to 3 years for PhD holders. This experience should encompass digital IC design, RTL development, and familiarity with ASIC design flows, as well as embedded systems development.

Languages:
Proficiency in spoken and written English is mandatory, and candidates should demonstrate a commitment to learning French. This bilingual capability is beneficial for effective communication within the diverse CERN community.

Additional Notes:
The contract duration for this position is 24 months, with the possibility of extension up to a maximum of 36 months. The working hours are set at 40 hours per week, and the job is fully onsite. The target start date for the position is October 1, 202

• The job reference number is EP-ESE-ME-2026-134-GRAP. The position offers a competitive monthly stipend ranging from 6,372 to 7,004 Swiss Francs, which is tax-free, along with 30 days of paid leave per year and additional benefits such as comprehensive health insurance coverage, family allowances, and a relocation package depending on individual circumstances. CERN also provides opportunities for on-the-job and formal training, including language classes.