ASIC Digital Designer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, is a leading scientific research organization established to probe the fundamental structure of the universe. It employs physicists and engineers who utilize the world's largest and most complex scientific instruments to study the basic constituents of matter. CERN's mission is to advance knowledge and understanding of the universe through cutting-edge research in particle physics. The organization has a diverse workforce and operates in multiple countries, welcoming applications from all Member States and Associate Member States. CERN is committed to diversity and inclusion, which are integral to its mission and success.

Job Overview:
The position of ASIC Digital Designer at CERN involves working on the development of Application-Specific Integrated Circuits (ASICs) for particle physics experiments. The successful candidate will be responsible for digital-on-top (DoT) implementation and System-on-Chip (SoC) design techniques, collaborating closely with system architects, analogue and mixed signal design teams, and verification engineers. The role is situated within the Electronic Systems for Experiments Group (ESE) of the Experimental Physics Department (EP), which is dedicated to designing electronic systems, including ASICs, for CERN's experiments. The Microelectronics section (ME) focuses on developing both analogue and digital ASICs for the readout and control of particle detector systems. The candidate will engage in full-chip digital integration and verification, ensuring that designs are synthesizable and reusable while applying low power design techniques.

Duties and Responsibilities:
As an ASIC Digital Designer, the candidate will perform a variety of tasks including full-chip digital integration and verification, which involves incorporating custom logic, third-party IP blocks, and standard interfaces. The role requires managing clock and reset domains and applying low power design techniques. The designer will develop RTL code to ensure that designs are synthesizable and reusable, and will create high-level architectures for ASIC designs, including SoC partitioning, data paths, control logic, and interfaces. Additionally, the candidate will write testbenches and run simulations to verify design functionality, ensuring that all aspects of the design meet the required specifications and performance metrics.

Required Qualifications:
Candidates must possess a Master's degree or PhD in Electronics Engineering or a related field, or have equivalent relevant experience. The position requires demonstrated experience in hierarchical Digital-On-Top ASIC integration and implementation, including functional and physical verification. Proven experience with advanced EDA tools and deep submicron CMOS technologies is essential, particularly with Cadence tools and process nodes such as 65nm, 28nm, or smaller. Candidates should also have experience in RTL design using Verilog/SystemVerilog and scripting languages such as Python, TCL, and Shell for workflow automation. Knowledge of integrating Analog and Digital IPs, managing interconnects, and planning clock/reset domains is also required.

Educational Background:
The educational background required for this position includes a Master's degree or PhD in Electronics Engineering or a closely related field. Candidates should have a strong foundation in electronics and microelectronics, with a focus on digital design and ASIC development. Relevant coursework and research experience in these areas will be beneficial for applicants.

Experience:
The ideal candidate should have substantial experience in the field of ASIC design, particularly in hierarchical Digital-On-Top ASIC integration and implementation. This includes experience from RTL to GDS, functional and physical verification, and familiarity with advanced EDA tools and deep submicron CMOS technologies. Candidates should also have a proven track record in RTL design, logic synthesis, timing closure, static timing analysis, and power integrity analysis, as well as experience in physical design floor planning, cell placement, routing, and sign-off checks.

Languages:
Fluency in spoken and written English is mandatory, and candidates should demonstrate a commitment to learning French. Proficiency in additional languages may be considered an asset, but English is the primary language of communication within CERN.

Additional Notes:
This position is a limited duration contract for 5 years, with the possibility of applying for an indefinite position subject to certain conditions. The working hours are set at 40 hours per week, and the role may involve working in radiation areas and during nights, Sundays, and official holidays as required by the needs of the organization. The job grade for this position is 6-7, and the job reference is EP-ESE-ME-2025-85-LD.