Digital ASIC Design Engineer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, is a leading scientific research institution established in 195

• It is located in Geneva, Switzerland, and is known for its groundbreaking work in particle physics. CERN employs thousands of scientists, engineers, and support staff from over 100 countries, fostering a collaborative environment that encourages innovation and scientific discovery. The organization operates numerous facilities and experiments, including the Large Hadron Collider, and is dedicated to pushing the boundaries of knowledge in the field of physics and technology. CERN's mission is to uncover the fundamental constituents of matter and the forces that govern their interactions, making it a hub for cutting-edge research and technological advancement.

Job Overview:
The Digital ASIC Design Engineer position at CERN involves working on the next generation of advanced MAPS (Monolithic Active Pixel Sensors) particle-detector ASICs. The successful candidate will play a crucial role in the design, implementation, and verification of high-performance digital readout and control circuits. This role requires a strong focus on meeting demanding targets related to speed, density, power efficiency, and radiation tolerance. The engineer will collaborate closely with specialists in analog design and verification, ensuring that the digital components integrate seamlessly with other parts of the system. The position also emphasizes teamwork, problem-solving, and knowledge sharing, as the engineer will be part of a multidisciplinary team dedicated to achieving results in a fast-paced research environment.

Duties and Responsibilities:
The duties and responsibilities of the Digital ASIC Design Engineer include:

• Conceiving and optimizing system-level architectures and data processing strategies to enhance performance and efficiency.
• Designing, synthesizing, and implementing RTL (Register Transfer Level) designs, ensuring timing closure and effective place and route of complex designs.
• Contributing to chip signoff through rigorous physical design checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC), as well as conducting power integrity analysis.
• Participating in formal verification processes using UVM (Universal Verification Methodology) methodologies to ensure the reliability and functionality of designs.
• Managing the complete RTL-to-GDS (Graphic Data System) flow and physical signoff utilizing professional EDA (Electronic Design Automation) tools.
• Collaborating and communicating effectively within a multidisciplinary team to achieve project goals.
• Engaging in continuous learning and knowledge sharing to solve problems and drive results through teamwork.

Required Qualifications:
Candidates must possess a professional background in Electronics Engineering or a related field. The qualifications include either a Master's degree with 2 to 6 years of post-graduation professional experience or a PhD with no more than 3 years of post-graduation professional experience. Additionally, candidates must not have previously held a CERN fellow or graduate contract. A strong understanding of VLSI (Very Large Scale Integration) principles and experience in digital IC design are essential for this role. Familiarity with digital or mixed-signal circuit design in ASICs or FPGAs is also required, along with experience in digital simulation techniques and tools being an advantage.

Educational Background:
The educational background required for this position includes a Master's degree or PhD in Electronics Engineering or a closely related field. The Master's degree should be complemented by 2 to 6 years of relevant professional experience, while a PhD should be accompanied by no more than 3 years of professional experience post-graduation. This educational foundation is critical for understanding the complexities of digital ASIC design and the associated engineering principles.

Experience:
The level of experience needed for this position includes a minimum of 2 years and a maximum of 6 years of post-graduation professional experience for candidates with a Master's degree. For those with a PhD, no more than 3 years of relevant experience is required. Candidates should have hands-on experience in digital IC design, particularly in the context of ASICs or FPGAs, and should be familiar with the latest design and verification methodologies.

Languages:
Proficiency in spoken and written English is mandatory for this position, as it is the primary language of communication at CERN. Additionally, candidates should demonstrate a commitment to learning French, which is beneficial for integration into the local community and workplace.

Additional Notes:
This position is offered on a hybrid basis, allowing for a combination of remote and on-site work. The contract duration is initially set for 24 months, with the possibility of extension up to a maximum of 36 months. The target start date for this role is February 1, 202

• The position may require work during nights, Sundays, and official holidays, depending on the needs of the organization. The job reference for this position is EP-ESE-ME-2025-225-GRAP. Compensation includes a monthly stipend ranging from 6287 to 6911 Swiss Francs, which is tax-free, along with 30 days of paid leave per year, comprehensive health insurance coverage, and various allowances based on individual circumstances. Additionally, a relocation package is available, and opportunities for on-the-job and formal training, including language classes, are provided.