ASIC Digital Designer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, is a leading scientific research institution established in 195

• It is headquartered in Geneva, Switzerland, and operates in multiple countries across Europe. CERN's mission is to push the frontiers of science and technology, particularly in the field of particle physics. The organization employs thousands of scientists, engineers, and support staff from diverse backgrounds, fostering an environment of innovation and collaboration. CERN is known for its groundbreaking work in understanding the fundamental laws of the universe through the design and operation of particle accelerators and experiments. The organization values diversity and inclusion, making it a core part of its mission and success.

Job Overview:
The ASIC Digital Designer position at CERN involves working within the HSE-TS-IMS Section, which is responsible for the design, development, installation, commissioning, operation, and maintenance of radiation monitoring equipment. This role is crucial for ensuring that CERN can operate its accelerator complex and related experiments while adhering to legal obligations for public and environmental safety. The successful candidate will be part of a team that is developing a new generation of ASICs to interface ionization chamber signals with safety-critical monitoring systems. The position requires collaboration with various teams to ensure system-level compatibility and involves hands-on experience with open-source ASIC EDA flows, RTL design, and post-fabrication validation.

Duties and Responsibilities:
As an ASIC Digital Designer, your responsibilities will include designing, simulating, and verifying the digital architecture of next-generation ASIC front-ends. You will prepare RTL designs for tapeout using open-source EDA flows, which includes floorplanning and physical design preparation. Additionally, you will support post-fabrication bring-up, system characterization, and functional/performance validation. Collaboration with analogue, verification, and SoC integration teams is essential to ensure seamless compatibility across systems. You will also be expected to contribute to the development of SoC submodules and engage in hardware debugging and prototype bring-up activities.

Required Qualifications:
Candidates must have hands-on experience with open-source ASIC EDA flows such as Yosys, OpenROAD, and LibreLane, covering the entire process from RTL to GDSII. Experience in floorplanning, constraint definition, and physical design preparation for tapeout is required. Post-tapeout prototype bring-up and hardware debugging experience is advantageous. Active contributions to open-source hardware projects or EDA toolchains are also beneficial. Candidates should possess skills in HDL design and simulation using VHDL, Verilog, or SystemVerilog, and should be proficient in Git, CI/CD pipelines, and automated verification workflows. Knowledge of RISC-V architecture and familiarity with mixed-signal integration and digital interface protocols is expected.

Educational Background:
The position requires candidates to hold a Bachelor's or Master's degree in Electronics or a related field. Applicants must be nationals of a CERN Member or Associate Member State and should have a maximum of two years of professional experience since graduation. It is important to note that applicants without a university degree or those with a PhD are not eligible for this position.

Experience:
Candidates should have a maximum of two years of professional experience in the field of Electronics or a related area since their graduation. This experience should ideally include hands-on work with ASIC design and development processes, as well as familiarity with the tools and methodologies used in the industry.

Languages:
Proficiency in spoken and written English is mandatory for this position. Candidates should also demonstrate a commitment to learning French, as it is beneficial for communication within the organization and the local community.

Additional Notes:
The contract duration for this position is 24 months, with a possibility of extension up to 36 months. The working hours are set at 40 hours per week, and the job offers a hybrid flexibility model. The target start date for the position is October 1, 202

• The job reference for this position is HSE-TS-IMS-2026-189-GRAE. Compensation includes a monthly stipend ranging from 5266 to 5793 Swiss Francs, which is tax-free, along with 30 days of paid leave per year and additional benefits such as health insurance coverage, family allowances, and a relocation package.