Digital ASIC Design Engineer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, is a leading scientific research institution established in 195

• It is located in Geneva, Switzerland, and is known for its groundbreaking work in particle physics. CERN employs thousands of scientists, engineers, and support staff from over 100 countries, fostering a collaborative environment that encourages innovation and scientific discovery. The organization operates numerous facilities and experiments, including the Large Hadron Collider, and is dedicated to pushing the frontiers of science and technology. CERN's mission is to uncover the fundamental structure of the universe and to advance knowledge through research and collaboration.

Job Overview:
The Digital ASIC Design Engineer position at CERN involves working on the next generation of advanced MAPS particle-detector ASICs. The successful candidate will be responsible for the design, implementation, and verification of high-performance digital readout and control circuits. This role requires collaboration with analog and verification specialists to meet demanding targets in speed, density, power efficiency, and radiation tolerance. The engineer will conceive and optimize system-level architectures and data processing strategies, design and synthesize RTL, and manage the full RTL-to-GDS flow and physical signoff using professional EDA tools. The position also emphasizes teamwork, problem-solving, and knowledge sharing within a multidisciplinary team, contributing to CERN's mission of advancing scientific research.

Duties and Responsibilities:
The duties and responsibilities of the Digital ASIC Design Engineer include:

• Conceiving and optimizing system-level architectures and data processing strategies for particle-detector ASICs.
• Designing, synthesizing, and implementing RTL, including ensuring timing closure and place & route of complex designs.
• Contributing to chip signoff through physical design checks such as DRC, LVS, and ERC, as well as conducting power integrity analysis.
• Participating in formal verification processes using UVM methodologies.
• Managing the complete RTL-to-GDS flow and physical signoff with professional EDA tools.
• Collaborating effectively within a multidisciplinary team to achieve project goals.
• Learning and sharing knowledge, solving problems, and achieving results through teamwork.
• Adapting to work during nights, Sundays, and official holidays as required by the organization's needs.

Required Qualifications:
Candidates must have a professional background in Electronics engineering or a related field. They should possess either a Master's degree with 2 to 6 years of post-graduation professional experience or a PhD with no more than 3 years of post-graduation professional experience. Additionally, candidates must not have previously held a CERN fellow or graduate contract. Proficiency in RTL design using hardware description languages such as Verilog/SystemVerilog or VHDL is essential, along with proficiency in scripting languages like Python, TCL, and Shell, as well as versioning tools like Git. Experience with functional verification methodologies and simulation tools is also advantageous.

Educational Background:
The educational background required for this position includes a Master's degree in Electronics engineering or a related field, or a PhD in a relevant discipline. Candidates should have a solid understanding of VLSI principles and experience in digital IC design, particularly in the design and implementation of digital or mixed-signal circuits in ASICs or FPGAs. A strong foundation in digital simulation techniques and tools is also beneficial.

Experience:
The position requires candidates to have a minimum of 2 years and a maximum of 6 years of post-graduation professional experience if they hold a Master's degree. For those with a PhD, no more than 3 years of post-graduation professional experience is acceptable. Experience in digital IC design and a strong understanding of VLSI principles are crucial for success in this role.

Languages:
Fluency in spoken and written English is mandatory for this position. Candidates should also demonstrate a commitment to learning French, as it is beneficial for communication within the organization and the local community.

Additional Notes:
The contract duration for this position is 24 months, with the possibility of extension up to a maximum of 36 months. The job offers a hybrid work flexibility, allowing for a combination of on-site and remote work. The target start date for the position is June 1, 202

• The role may require work during nights, Sundays, and official holidays based on the organization's needs. The job reference is EP-ESE-ME-2025-225-GRAP, and it falls under the field of Electrical or Electronics Engineering. The compensation includes a monthly stipend ranging from 6372 to 7004 Swiss Francs, which is tax-free, along with 30 days of paid leave per year, comprehensive health insurance coverage, family allowances, and a relocation package depending on individual circumstances. Additionally, on-the-job and formal training, including language classes, will be provided.