Digital ASIC Design Engineer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, was established in 1954 and is one of the world's largest and most respected centers for scientific research. With a mission to probe the fundamental structure of the universe, CERN employs thousands of scientists, engineers, and support staff from over 100 countries. The organization operates in multiple countries and is known for its groundbreaking work in particle physics, utilizing the world's largest and most complex scientific instruments to study the basic constituents of matter. CERN's commitment to diversity and inclusion is a core value, ensuring a collaborative and innovative work environment.

Job Overview:
The Digital ASIC Design Engineer position at CERN involves working on the next generation of advanced MAPS particle-detector ASICs for the CERN detector complex. The role requires a strong focus on the design, implementation, and verification of high-performance digital readout and control circuits that must meet stringent targets in speed, density, power efficiency, and radiation tolerance. The engineer will collaborate closely with analog and verification specialists, contributing to the overall success of the projects. This position is ideal for individuals who are passionate about electronics engineering and eager to work in a multidisciplinary team environment, where learning and knowledge sharing are highly encouraged. The engineer will be expected to manage the full RTL-to-GDS flow and physical signoff using professional EDA tools, ensuring that all designs meet the required specifications and standards.

Duties and Responsibilities:
The duties and responsibilities of the Digital ASIC Design Engineer include:

• Conceiving and optimizing system-level architectures and data processing strategies to enhance performance.
• Designing, synthesizing, and implementing RTL, including achieving timing closure and place & route of complex designs.
• Contributing to chip signoff through conducting physical design checks such as DRC, LVS, and ERC, as well as performing power integrity analysis.
• Participating in formal verification processes using UVM methodologies to ensure design correctness.
• Managing the complete RTL-to-GDS flow and physical signoff with the use of professional EDA tools.
• Collaborating and communicating effectively within a multidisciplinary team to achieve project goals.
• Engaging in continuous learning and knowledge sharing to solve problems and achieve results through teamwork.
• Adapting to work during nights, Sundays, and official holidays as required by the needs of the organization.

Required Qualifications:
Candidates must have a professional background in Electronics engineering or a related field. The position requires either a Master's degree with 2 to 6 years of post-graduation professional experience or a PhD with no more than 3 years of post-graduation professional experience. Additionally, candidates must not have previously held a CERN fellow or graduate contract. A strong understanding of VLSI principles and experience in digital IC design are essential, along with familiarity with digital or mixed-signal circuits in ASICs or FPGAs. Experience with digital simulation techniques and tools is considered an advantage.

Educational Background:
The educational background required for this position includes a Master's degree or PhD in Electronics engineering or a closely related field. The educational qualifications should be complemented by relevant professional experience in the field of digital IC design, ensuring that candidates possess the necessary theoretical knowledge and practical skills to excel in this role.

Experience:
The level of experience needed for the Digital ASIC Design Engineer position includes a minimum of 2 years and a maximum of 6 years of post-graduation professional experience for candidates with a Master's degree. For those with a PhD, no more than 3 years of post-graduation professional experience is required. Candidates should have hands-on experience in digital IC design and a solid understanding of VLSI principles, as well as familiarity with the design and implementation of digital or mixed-signal circuits in ASICs or FPGAs.

Languages:
Proficiency in spoken and written English is mandatory for this position, as it is the primary language of communication at CERN. Additionally, candidates should demonstrate a commitment to learning French, which is considered beneficial for integration into the workplace and the local community. Knowledge of other languages may also be advantageous but is not a requirement.

Additional Notes:
The contract duration for this position is 24 months, with the possibility of extension up to a maximum of 36 months. The job offers a hybrid work flexibility, allowing for a combination of remote and on-site work. The target start date for the position is February 1, 202

• The role may require working during nights, Sundays, and official holidays based on the organization's needs. The compensation includes a monthly stipend ranging from 6287 to 6911 Swiss Francs per month, net of tax, along with comprehensive health coverage for the employee and their family, membership in the CERN Pension Fund, and various allowances depending on individual circumstances. Employees are entitled to 30 days of paid leave per year and will have access to on-the-job and formal training opportunities, as well as in-house language courses for English and/or French.