Digital ASIC Designer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, was established in 1954 and is one of the world's largest and most respected centers for scientific research. With a mission to push the frontiers of science and technology, CERN employs thousands of professionals from various fields, including physics, engineering, and administration. The organization operates in multiple countries and is known for its collaborative environment that fosters innovation and diversity. CERN's work is pivotal in advancing our understanding of the universe, and it continues to attract talent from around the globe to contribute to groundbreaking research.

Job Overview:
The Digital ASIC Designer position at CERN's EP-ESE-ME section involves the development of a radiation-tolerant microcontroller ASIC intended for future particle physics detectors and accelerator systems. The role requires the successful candidate to engage in the entire development cycle, which includes defining requirements, system architecture, implementation, verification, and post-silicon validation. The project utilizes an open-source RISC-V processing core and the CERN SOCRATES framework, emphasizing the need for robust and reliable embedded electronics capable of operating in challenging radiation environments. The candidate will analyze application requirements, contribute to the design and validation of the ASIC, and apply fault-tolerant design methodologies, ensuring the microcontroller meets the rigorous standards necessary for particle physics applications.

Duties and Responsibilities:
The responsibilities of the Digital ASIC Designer include analyzing application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC. The designer will contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology. They will support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core. The role also involves designing, integrating, and validating peripheral IP blocks within the CERN SOCRATES framework, applying fault-tolerant design methodologies such as triple modular redundancy (TMR) and single-event upset (SEU) mitigation techniques. Additionally, the designer will participate in design verification activities and physical implementation, from RTL development through to tapeout, and contribute to post-silicon testing, characterization, and validation following chip fabrication.

Required Qualifications:
Candidates must possess a strong understanding of digital logic design and solid experience with digital IC design and RTL development, specifically in Verilog/SystemVerilog. Familiarity with standard ASIC design flows, including synthesis, place and route, and timing closure, is essential. Knowledge of RISC-V architecture and its ecosystem, as well as experience with microcontroller-based embedded systems development, including firmware programming in C and peripheral interfacing, is required. Additional skills include RTL design and simulation, familiarity with fault-tolerant design techniques, and scripting and automation capabilities, preferably in Python or equivalent. A willingness to learn in a multidisciplinary environment and the ability to work both independently and as part of a team are also important.

Educational Background:
The position requires candidates to have a professional background in Electronics Engineering or a related field. Applicants should hold either a Master's degree with 2 to 6 years of post-graduation professional experience or a PhD with no more than 3 years of post-graduation professional experience. It is also necessary that candidates have never held a CERN fellow or graduate contract before.

Experience:
Candidates should have a professional background that includes significant experience in digital IC design and RTL development. The ideal applicant will have a minimum of 2 years of relevant experience post-graduation for those with a Master's degree, or up to 3 years for those with a PhD. Experience in working with microcontroller-based embedded systems and familiarity with ASIC design flows is highly desirable.

Languages:
Fluency in spoken and written English is mandatory, with a commitment to learn French being an asset. Proficiency in additional languages may be beneficial but is not required.

Additional Notes:
The contract duration for this position is 24 months, with the possibility of extension up to a maximum of 36 months. The working hours are set at 40 hours per week, and the position is fully onsite. The target start date for the role is January 1, 202

• The job reference is EP-ESE-ME-2026-134-GRAP. Compensation includes a monthly net stipend ranging from 6372 to 7004 Swiss Francs, depending on the candidate's degree. Additional benefits include 30 days of paid leave per year, comprehensive health insurance coverage, family allowances, a relocation package, and opportunities for on-the-job and formal training, including language classes.