FPGA / SoC Gateware Engineer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, is a leading scientific research institution established in 195

• It is headquartered in Geneva, Switzerland, and employs over 2,500 staff members, along with thousands of scientists and engineers from around the world. CERN's mission is to explore the fundamental structure of the universe through high-energy particle physics, utilizing the world's largest and most complex scientific instruments. The organization operates in multiple countries, collaborating with various international institutions and universities to advance scientific knowledge and innovation in the field of particle physics.

Job Overview:
As an FPGA / SoC Gateware Engineer at CERN, you will be part of a dynamic team dedicated to the design and support of power converter controls for CERN's accelerator systems. This role requires a blend of creativity and technical expertise, particularly in programmable technologies such as FPGAs and SoCs. You will be responsible for developing gateware solutions that meet user requirements and managing existing platforms. Your contributions will directly impact the efficiency and effectiveness of CERN's operations, as you work on both current and next-generation systems. The position offers an opportunity to engage in ambitious R&D programs and collaborate with experts in the field, making it a pivotal role within the Accelerator Systems Department.

Duties and Responsibilities:
In your role as an FPGA / SoC Gateware Engineer, you will undertake a variety of responsibilities, including but not limited to: designing and simulating modular programmable electronic device IP cores, particularly focusing on newer systems based on SoC architectures like Zynq UltraScale+ and existing systems utilizing SRAM and FLASH FPGAs. You will establish and maintain code versioning systems using Git, implement Continuous Integration and Deployment (CI/CD) systems, and ensure the testing and validation of code releases. Additionally, you will supervise a team of graduates, define requirements, and provide comprehensive user and expert documentation. Your role will also involve testing, commissioning, and supporting the operation of controls electronics, ensuring that all systems function optimally and meet the high standards expected at CERN.

Required Qualifications:
Candidates must possess a Master's degree or PhD in electronic engineering, computer engineering, embedded systems, or a related field, with a strong emphasis on FPGA design, SoC architecture, and digital hardware design. Proven experience in SoC/FPGA technology is essential, particularly with Xilinx/AMD SoCs and FPGAs. Familiarity with gateware architectures and DevOps practices is also required. Additionally, candidates should demonstrate initial experience in supervising a small team, showcasing leadership potential and the ability to guide less experienced engineers in their work.

Educational Background:
The ideal candidate will have a Master's degree or PhD in electronic engineering, computer engineering, embedded systems, or a closely related discipline. This educational background should include a focus on FPGA design, SoC architecture, and digital hardware design, equipping the candidate with the necessary theoretical and practical knowledge to excel in this role.

Experience:
Candidates should have proven experience in SoC/FPGA technology, particularly with Xilinx/AMD devices. This includes a solid understanding of gateware architectures and the ability to effectively utilize this technology in practical applications. Experience in Gateware DevOps is also a critical requirement, as is initial experience in supervising a small team, which demonstrates the candidate's capability to lead and mentor others in a technical environment.

Languages:
Fluency in spoken and written English is mandatory, and proficiency in French is highly desirable. Candidates should also demonstrate a commitment to learning the other language, as effective communication in both languages is essential for collaboration within the diverse environment at CERN.

Additional Notes:
This position is offered as a limited duration contract for 5 years, with the possibility of applying for an indefinite position subject to certain conditions. The role requires a commitment of 40 hours per week and includes participation in a regular stand-by duty, which may involve working nights, Sundays, and official holidays. The job grade for this position is classified as 6-7, and the job reference is SY-EPC-CCE-2025-107-LD. CERN values diversity and encourages applications from all Member States and Associate Member States.