FPGA / SoC Gateware Engineer

Job Posting Organization:
CERN, the European Organization for Nuclear Research, is a leading scientific research organization established to probe the fundamental structure of the universe. Founded in 1954, CERN employs thousands of scientists and engineers from various countries, making it a hub for international collaboration in particle physics. The organization operates in multiple countries and is known for its cutting-edge research and development in the field of nuclear and particle physics, utilizing the world's largest and most complex scientific instruments to study fundamental particles and their interactions.

Job Overview:
As an FPGA / SoC Gateware Engineer at CERN, you will be part of a dynamic team dedicated to the design and support of power converter controls for CERN's accelerator systems. This role requires a blend of creativity and technical expertise in gateware DevOps, particularly with programmable technologies such as FPGAs and SoCs. You will be responsible for collaborating with users to develop gateware solutions, managing existing platforms, and leading a team of graduates. Your contributions will directly impact the efficiency and effectiveness of CERN's operations, ensuring that beam delivery to users is optimized. The position offers an exciting opportunity to work on both current and next-generation systems, contributing to ambitious R&D programs within the Accelerator Systems Department.

Duties and Responsibilities:
In your role as FPGA / SoC Gateware Engineer, you will engage in a variety of tasks including: designing and simulating modular programmable electronic device IP cores; working with both existing FPGA systems and newer SoC-based systems; establishing and maintaining code versioning systems using Git; implementing Continuous Integration and Deployment (CI/CD) systems; testing and validating code releases to ensure coherence; supervising a team of graduates; defining requirements and creating user documentation; and supporting the commissioning and operation of controls electronics. Your work will encompass the entire lifecycle of gateware development, from initial design through to long-term support and maintenance.

Required Qualifications:
Candidates must possess a Master's degree or PhD in electronic engineering, computer engineering, embedded systems, or a related field, with a strong focus on FPGA design, SoC architecture, and digital hardware design. Proven experience in SoC/FPGA technology, particularly with Xilinx/AMD products, is essential. Additionally, candidates should have demonstrated experience in gateware DevOps and initial supervisory experience with a small team. Technical competencies should include design and simulation of FPGA-based electronics, knowledge of high-level description languages, and familiarity with software life-cycle tools and procedures.

Educational Background:
The ideal candidate will have a Master's degree or PhD in a relevant field such as electronic engineering, computer engineering, or embedded systems. This educational background should include a focus on FPGA design and SoC architecture, equipping the candidate with the necessary theoretical and practical knowledge to excel in the role.

Experience:
Candidates should have proven experience in SoC/FPGA technology, particularly with Xilinx/AMD SoC and FPGA. This includes the ability to define gateware architectures that effectively utilize this technology. Experience in gateware DevOps is also required, along with initial experience in supervising a small team, demonstrating leadership capabilities in a technical environment.

Languages:
Fluency in spoken and written English or French is mandatory, with a commitment to learn the other language being highly desirable. This bilingual requirement reflects CERN's diverse and international working environment, where effective communication across languages is essential.

Additional Notes:
The position is a limited duration contract for 5 years, with the possibility of applying for an indefinite position subject to certain conditions. The working hours are set at 40 hours per week, and the role includes participation in a regular stand-by duty, which may involve nights, Sundays, and official holidays. The job grade is classified as 6-7, and the job reference is SY-EPC-CCE-2025-107-LD. CERN values diversity and encourages applications from all Member States and Associate Member States.